(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a dynamic random access memory, (DRAM), device, with increased capacitance, resulting via the use of a novel configuration for the storage node structure, of a stacked capacitor structure.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still maintaining, or even decreasing the manufacturing cost of these same semiconductor devices. The advent of micro-miniaturization, or the ability to fabricate semiconductor devices, with sub-micron features, has allowed the industry's performance and cost objectives to be successfully addressed. The use of sub-micron features result in decreases in performance degrading capacitances and resistances, thus allowing improved device performance to be realized. In addition the use of micro-miniaturization allows smaller chips, still containing circuit densities comparable to circuit densities obtained with larger semiconductor chips, to be fabricated. This in turn results in an increase in the amount of semiconductor chips obtained from a specific size starting substrate, thus resulting in a reduction of manufacturing cost of a specific chip.
Dynamic random access memory, (DRAM), devices, are being fabricated using a stacked capacitor, (STC), structure, overlying a transfer gate transistor. The shrinking of device features has resulted in a decrease in STC dimensions, therefore the capacitance of the STC structure, influenced by the dimensions of the storage node electrode, has to be increased via other means. The use of thinner capacitor dielectric layers, or of higher dielectric constant materials, used to increase STC capacitance, is limited by process complexity or yield concerns. Therefore the DRAM community has focused on capacitance increases via the creation of storage node electrodes, exhibiting unique configurations, such as a polysilicon storage node electrode, featuring horizontal and vertical polysilicon shapes, resulting in an increase in surface area when compared to counterparts, fabricated without the vertical and horizontal polysilicon features. For example prior art, such as Taguchi, et al, in U.S. Pat. No. 4,974,040, describe a polysilicon storage node electrode, fabricated using several stacked conductive layers. In addition Chen, et al, in U.S. Pat No. 5,116,776, also describe a polysilicon storage node electrode, configured to include stacked, horizontal features, again increasing the surface area of the storage node structure, when compared to configurations created without the stacked horizontal, polysilicon features.
This invention will describe a novel configuration for a polysilicon storage node electrode, characterized by several stacked, horizontal polysilicon features, however also characterized by vertical polysilicon features, each attached to a horizontal polysilicon feature, thus offering a larger surface area increase, than surface area enhancements obtained with counterparts fabricated without the vertical polysilicon feature. In addition this invention will describe a novel fabrication process, needed to create the unique, polysilicon storage node electrode configuration. The novel fabrication procedure features a process step designed to allow regions of insulator to remain, between horizontal polysilicon features, needed to physically support this polysilicon, storage node electrode configuration.